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1 ? fn8173.4 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas inc. copyright intersil americas inc. 2005, 2006, 2007. all rights reserved all other trademarks mentioned are the property of their respective owners. x9269 single supply/low powe r/256-tap/2-wire bus dual digitally-controlled (xdcp?) potentiometers features ? dual?two separate potentiometers ? 256 resistor taps/pot?0.4% resolution ? 2-wire serial interface for write, read, and transfer operations of the potentiometer single supply device ? wiper resistance, 100 typical v cc = 5v ? 4 nonvolatile data registers for each potentiometer ? nonvolatile storage of multiple wiper positions ? power-on recall. loads saved wiper position on power-up. ? standby current < 5a max ?50k , 100k versions of end to end pot resistance ? 100 yr. data retention ? endurance: 100,000 data changes per bit per register ? 24-lead soic, 24-lead tssop ? low power cmos ? power supply v cc = 2.7v to 5.5v ? pb-free plus anneal available (rohs compliant) description the x9269 integrates 2 digitally controlled potentiometer (xdcp) on a monolithic cmos integrated circuit. the digital controlled poten tiometer is implemented using 255 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the 2-wire bus interface. each potentiometer has associated with it a volatile wiper counter register (wcr) and a four nonvolatile data registers that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array though the switches. powerup recalls the contents of the default data register (dr0) to the wcr. the xdcp can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. functional diagram r h0 r l0 r w0 v cc v ss 2-wire bus 50k or 100k versions r h1 r l1 r w1 power-on recall wiper counter registers (wcr) data registers (dr0?dr3) interface bus interface and control address data status write read transfer inc/dec control data sheet april 17, 2007 n o t r e c o m m e n d e d f o r n e w d e s i g n s p o s s i b l e s u b s t i t u t e p r o d u c t x 9 5 8 2 0
2 fn8173.4 april 17, 2007 ordering information part number part marking v cc limits (v) potentiometer organization (k ) temp range (c) package pkg. dwg. # x9269ts24* x9269ts 5 10% 100 0 to +70 24 ld soic (300 mil) m24.3 x9269ts24i* x9269ts i -40 to +85 24 ld soic (300 mil) m24.3 x9269ts24iz* (note) x9269ts zi -40 to +85 24 ld soic (300 mil) (pb-free) m24.3 x9269ts24z* (note) x9269ts z 0 to +70 24 ld soic (300 mil) (pb-free) m24.3 x9269tv24 x9269tv 0 to +70 24 ld tssop (4.4mm) mdp0044 x9269us24* x9269us 50 0 to +70 24 ld soic (300 mil) m24.3 x9269us24i* x9269us i -40 to +85 24 ld soic (300 mil) m24.3 x9269us24iz* (note) x9269us zi -40 to +85 24 ld soic (300 mil) (pb-free) m24.3 x9269us24z* (note) x9269us z 0 to +70 24 ld soic (300 mil) (pb-free) m24.3 x9269uv24* x9269uv 0 to +70 24 ld tssop (4.4mm) mdp0044 x9269uv24i x9269uv i -40 to +85 24 ld tssop (4.4mm) mdp0044 x9269ts24-2.7* x9269ts f 2.7 to 5.5 100 0 to +70 24 ld soic (300 mil) m24.3 x9269ts24i-2.7* x9269ts g -40 to +85 24 ld soic (300 mil) m24.3 x9269ts24iz-2.7* (note) x9269ts zg -40 to +85 24 ld soic (300 mil) (pb-free) m24.3 x9269ts24z-2.7* (note) x9269ts zf 0 to +70 24 ld soic (300 mil) (pb-free) m24.3 x9269tv24i-2.7 x9269tv g -40 to +85 24 ld tssop (4.4mm) mdp0044 x9269tv24iz-2.7* (note) x9269tv zg -40 to +85 24 ld tssop (4.4mm) (pb-free) mdp0044 x9269us24-2.7* x9269us f 50 0 to +70 24 ld soic (300 mil) m24.3 x9269us24i-2.7* x9269us g -40 to +85 24 ld soic (300 mil) m24.3 x9269us24iz-2.7* (note) x9269us zg -40 to +85 24 ld soic (300 mil) (pb-free) m24.3 x9269us24z-2.7* (note) x9269us zf 0 to +70 24 ld soic (300 mil) (pb-free) m24.3 x9269uv24-2.7* x9269uv f 0 to +70 24 ld tssop (4.4mm) mdp0044 x9269uv24i-2.7* x9269uv g -40 to +85 24 ld tssop (4.4mm) mdp0044 x9269uv24iz-2.7* x9269uv zg -40 to +85 24 ld tssop (4.4mm) mdp0044 *add "t1" suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. x9269
3 fn8173.4 april 17, 2007 detailed functional diagram circuit level applications ? vary the gain of a voltage amplifier ? provide programmable dc reference voltages for comparators and detectors ? control the volume in audio circuits ? trim out the offset voltage error in a voltage amplifier circuit ? set the output voltage of a voltage regulator ? trim the resistance in wheatstone bridge circuits ? control the gain, characteristic frequency and q-factor in filter circuits ? set the scale factor and zero point in sensor signal conditioning circuits ? vary the frequency and duty cycle of timer ics ? vary the dc biasing of a pin diode attenuator in rf circuits ? provide a control variable (i, v, or r) in feedback circuits system level applications ? adjust the contrast in lcd displays ? control the power level of led transmitters in communication systems ? set and regulate the dc biasing point in an rf power amplifier in wireless systems ? control the gain in audio and home entertainment systems ? provide the variable dc bias for tuners in rf wireless systems ? set the operating points in temperature control systems ? control the operating point for sensors in industrial systems ? trim offset and gain errors in artificial intelligent systems interface and control circuitry a0 scl sda a1 a2 wp a3 v cc v ss r 0 r 1 r 2 r 3 wiper counter register (wcr) resistor array pot 1 r 0 r 1 r 2 r 3 wiper counter register (wcr) data 8 pot 0 power-on recall power-on recall r h0 r l0 r w0 r h1 r l1 r w1 256-taps 50k and 100k x9269
4 fn8173.4 april 17, 2007 pin configuration pin assignments nc a0 nc nc v cc r l0 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 a3 scl nc nc nc nc v ss r w1 r h1 r l1 soic/tssop x9269 nc 14 13 11 12 nc r h0 r w0 a2 a1 sda wp pin (soic/tssop) symbol function 1 nc no connect 2 a0 device address for 2-wire bus. 3 nc no connect 4 nc no connect 5 nc no connect 6 nc no connect 7v cc system supply voltage 8r l0 low terminal for potentiometer 0. 9r h0 high terminal for potentiometer 0. 10 r w0 wiper terminal for potentiometer 0. 11 a2 device address for 2-wire bus. 12 wp hardware write protect 13 sda serial data input/output for 2-wire bus. 14 a1 device address for 2-wire bus. 15 r l1 low terminal for potentiometer 1. 16 r h1 high terminal for potentiometer 1. 17 r w1 wiper terminal for potentiometer 1. 18 v ss system ground 19 nc no connect 20 nc no connect 21 nc no connect 22 nc no connect 23 scl serial clock for 2-wire bus. 24 a3 device address for 2-wire bus. x9269
5 fn8173.4 april 17, 2007 pin descriptions bus interface pins s erial d ata i nput /o utput (sda) the sda is a bidirectional se rial data input/output pin for a 2-wire slave device and is used to transfer data into and out of the device. it receives device address, opcode, wiper register address and data sent from an 2-wire master at the rising edge of the serial clock scl, and it shifts out data after each falling edge of the serial clock scl. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for sele cting typical valu es, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. s erial c lock (scl) this input is used by 2-wire master to supply 2-wire serial clock to the x9269. d evice a ddress (a3 - a0) the address inputs are used to set the least significant 4 bits of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the x9269. a maximum of 16 devices may occupy the 2-wire serial bus. potentiometer pins r h , r l the r h and r l pins are equivalent to the terminal connections on a mechanical potentiometer. since there are 2 potentiometers, there are 2 sets of r h and r l such that r h0 and r l0 are the terminals of pot 0 and so on. r w the wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. since there are 4 potentiometers, there are 2 sets of r w such that r w0 is the terminal of pot 0 and so on. bias supply pins s ystem s upply v oltage (v cc ) and s upply g round (v ss ) the v cc pin is the system supply voltage. the v ss pin is the system ground. other pins n o c onnect no connect pins should be left open. this pins are used for intersil manufacturing and testing purposes. h ardware w rite p rotect i nput (wp ) the wp pin when low prevents nonvolatile writes to the data registers. x9269
6 fn8173.4 april 17, 2007 principles of operation the x9269 is a integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the digitally controlled potentiometers. this section provides detail description of the following: ? resistor array description ? serial interface description ? instruction and register description. array description the x9269 is comprised of a resistor array (see figure 1). each array contains 255 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l inputs). at both ends of each arra y and between each resistor segment is a cmos switch connected to the wiper (r w ) output. within each individual array only one switch may be turned on at a time. these switches are cont rolled by a wiper counter register (wcr). the 8-bits of the wcr (wcr[7:0]) are decoded to select, and enable, one of 256 switches (see table 1). the wcr may be written directly. these data registers can the wcr can be read and written by the host system. power-up and down requirements. there are no restrictions on the power-up or power- down conditions of v cc and the voltages applied to the potentiometer pins provided that v cc is always more positive than or equal to v h , v l , and v w , i.e., v cc v h , v l , v w . the v cc ramp rate specification is always in effect. figure 1. detailed potentiometer block diagram serial data path from interface circuitry register 0 register 1 register 2 register 3 serial bus input parallel bus input counter register inc/dec logic up/dn clk modified scl up/dn r h r l r w 8 8 c o u n t e r d e c o d e if wcr = 00[h] then r w = r l if wcr = ff[h] then r w = r h wiper (wcr) one of two potentiometers (dr0) (dr1) (dr2) (dr3) x9269
7 fn8173.4 april 17, 2007 serial interface description serial interface the x9269 supports a bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will alwa ys initiate da ta transfers and provide the clock for both transmit and receive operations. therefore, the x9269 will be considered a slave device in all applications. clock and data conventions data states on the sda line can change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop conditions. see figure 2. start condition all commands to the x9269 are preceded by the start condition, which is a high to low transition of sda while scl is high. the x9269 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition is met. see figure 2. stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda while scl is high. see figure 2. acknowledge acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. the transmitting device, either the master or the slave, will release the sda bu s after transmitting eight bits. the master generates a ninth clock cycle and during this period the receiver pulls the sda line low to acknowledge that it successfully received the eight bits of data. the x9269 will respond wit h an ackno wledge after recognition of a start cond ition and its slave address and once again after successful receipt of the command byte. if the command is followed by a data byte the x9269 will respond with a final acknowledge. see figure 2. figure 2. acknowledge response from receiver scl from master data output from transmitter 1 89 data output from receiver start acknowledge x9269
8 fn8173.4 april 17, 2007 acknowledge polling the disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typica l 5ms eeprom write cycle time. once the stop condition is issued to indicate the end of the nonvolatile write command the x9269 initiates the internal writ e cycle. ack polling, flow 1, can be initiated immediately. this involves issuing the start condition followed by t he device slave address. if the x9269 is still busy with the write oper ation no ack will be returned. if the x926 9 has completed the write operation an ack will be re turned and th e master can then proceed with the next operation. flow 1: ack polling sequence instruction and register description instructions d evice a ddressing : i dentification b yte (id and a) the first byte sent to the x9269 from the host is called the identification byte. the mo st significant four bits of the slave address are a dev ice type identifier. the id[3:0] bits is the device id for the x9269; this is fixed as 0101[b] (refer to table 1). the a[3:0] bits in the id byte is the internal slave address. the physical device address is defined by the state of the a3-a0 input pins. the slave address is externally specified by the user. the x9269 compares the serial data stream with the address input state; a successful compare of both address bits is required for the x9269 to successfully continue the command sequence. only the device which slave address matches the incoming device address sent by the master executes the instruction. the a3 - a0 inputs can be actively driven by cmos input signals or tied to v cc or v ss . i nstruction b yte (i) the next byte sent to the x9269 contains the instruction and register pointer information. the three most significant bits are used provide the instruction opcode i [3:0]. the rb and ra bits point to one of the four data registers of each associated xdcp. the least significant bit points to one of two wiper counter registers or pots. the format is shown in table 2. register selection nonvolatile write command completed enterack polling issue start issue slave address ack returned? further operation? issue instruction issue stop no yes yes proceed issue stop no proceed register selected rb ra dr0 0 0 dr1 0 1 dr2 1 0 dr3 1 1 x9269
9 fn8173.4 april 17, 2007 table 1. identification byte format table 2. instruction byte format table 3. instruction set note: 1/0 = data is one or zero id3 id2 id1 id0 a3 a2 a1 a0 0101 (msb) (lsb) device type identifier slave address i3 i2 i1 i0 rb ra 0 p0 (msb) (lsb) instruction register pot selection opcode selection (wcr selection) instruction instruction set operation i3 i2 i1 i0 rb ra 0 p0 read wiper counter register 100100 01/0r ead the contents of the wiper counter register pointed to by p0 write wiper counter register 101000 01/0write new value to the wiper c ounter register pointed to by p0 read data register 10111/01/001/0r ead the contents of the data register pointed to by p0 and rb - ra write data register 11001/01/001/0write new value to the data register pointed to by p0 and rb - ra xfr data register to wiper counter register 11011/01/001/0transfer the contents of the data register pointed to by p0 and rb - ra to its associated wiper counter register xfr wiper counter register to data register 11101/01/001/0transfer the contents of the wiper c ounter register pointed to by p0 to the data register pointed to by rb - ra global xfr data registers to wiper counter registers 00011/01/00 0transfer the contents of the data registers pointed to by rb - ra of all four pots to their respective wiper counter registers global xfr wiper counter registers to data register 10001/01/00 0transfer the contents of both wiper counter registers to their respective data registers pointed to by rb - ra of all four pots increment/decrement wiper counter register 001000 01/0enable increment/decrement of the control latch pointed to by p0 x9269
10 fn8173.4 april 17, 2007 device description wiper counter register (wcr) the x9269 contains two wiper counter registers, one for each dcp potentiometer. the wiper counter register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written directly by the host via the write wiper counter register in struction (serial load); it may be written indirectly by transfer ring the contents of one of four associated data registers via the xfr data register instruction (paralle l load); it can be modified one step at a time by the increment/decrement instruction (see instructio n section for more details). finally, it is loaded with the contents of its data register zero (dr0) upon power-up. the wiper counter register is a volatile register; that is, its contents are lost when the x9269 is powered- down. although the register is automatically loaded with the value in dr0 upon power-up, this may be different from the value present at power-down. power-up guidelines are recommended to ensure proper loadings of the dr0 value into the wcr (see design considerations section). data registers (dr) each potentiometer has four 8-bit nonvolatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the associated wiper counter register. all operations changing data in one of the data registers is a nonvolat ile operation and will take a maximum of 10ms. if the application does not require storage of multiple settings for the potentiomete r, the data registers can be used as regular memory locations for system parameters or user preference data. bit [7:0] are used to store one of the 256 wiper positions (0~255). table 4. wiper counter register, wcr (8-bit), wcr[7:0]: used to store the current wiper position (volatile, v). table 5. data register, dr (8-bit), bit [7:0]: used to store wiper positions or data (nonvolatile, nv). wcr7 wcr6 wcr5 wcr4 wcr3 wcr2 wcr1 wcr0 vvvvvvvv (msb) (lsb) bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 nv nv nv nv nv nv nv nv msb lsb x9269
11 fn8173.4 april 17, 2007 device description instructions four of the nine instructions are three bytes in length. these instructions are: ? read wiper counter register ? read the current wiper position of the selected potentiometer, ? write wiper counter register ? change current wiper position of the selected potentiometer, ? read data register ? read the contents of the selected data register; ? write data register ? write a new value to the selected data register. the basic sequence of the th ree byte instructions is illustrated in figure 4. th ese three-byte instructions exchange data between the wcr and one of the data registers. a transfer from a data register to a wcr is essentially a write to a static ram, with the static ram controlling the wiper positio n. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. four instructions require a two-byte sequence to complete. these instructions transfer data between the host and the x9269; either between the host and one of the data registers or directly between the host and the wiper counter register. these instructions are: ? xfr data register to wiper counter register ? this transfers the contents of one specified data register to the associated wiper counter register. ? xfr wiper counter regist er to data register ? this transfers the contents of the specified wiper counter register to the specified associated data register. ? global xfr data register to wiper counter register ? this transfers the contents of all speci- fied data registers to the associated wiper counter registers. ? global xfr wiper counter register to data register ? this transfers the contents of all wiper counter registers to the specified associated data registers. increment/decrement command the final command is increment/decrement (figure 5 and 6). the increment/decrement command is different from the other commands. once the command is issued and the x9269 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capab ility to the host. for each scl clock pulse (t high ) while sda is high, the selected wiper will move one resistor segment towards the r h terminal. similarly, for each scl clock pulse while sda is low, the selected wiper will move one resistor segment towards the r l terminal. see instruction format for more details. x9269
12 fn8173.4 april 17, 2007 figure 3. two-byte instruction sequence figure 4. three-byte instruction sequence figure 5. increment/decrement instruction sequence figure 6. increment/decrement timing limits s t a r t 0101 a2 a0 a c k i2 i1 i0 rb ra 0 a c k scl sda s t o p id3 id2 id1 id0 p0 device id external instruction opcode address register address pot/wcr address a1 a3 i3 i3 i2 i1 i0 rb ra id3 id2 id1 id0 device id external instruction opcode address register address pot/wcr address wcr[7:0] or data register d[7:0] s t a r t 0101 a2 a1 a0 a c k 0p0 a c k scl sda s t o p a c k d7 d6 d5 d4 d3 d2 d1 d0 a3 0 i3 i2 i1 i0 id3 id2 id1 id0 device id external instruction opcode address register address pot/wcr address s t a r t 0101 a2 a1 a0 a c k ra 0 p0 a c k scl sda s t o p i n c 1 i n c 2 i n c n d e c 1 d e c n rb a3 0 scl sda r w inc/dec cmd issued voltage out t wrid x9269
13 fn8173.4 april 17, 2007 instruction format read wiper counter register (wcr) write wiper counter register (wcr) read data register (dr) write data register (dr) global xfr data register (dr) to wiper counter register (wcr) s t a r t device type identifier device addresses s a c k instruction opcode dr/wcr addresses s a c k wiper position (sent by x9269 on sda) m a c k s t o p 0101a3a2a1a0 100100 0 p0 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t device type identifier device addresses s a c k instruction opcode dr/wcr addresses s a c k wiper position (sent by master on sda) s a c k s t o p 0101a3a2a1a0 101000 0 p0 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t device type identifier device addresses s a c k instruction opcode dr/wcr addresses s a c k wiper position (sent by x9269 on sda) m a c k s t o p 0 1 0 1a3a2a1a0 1011rbra 0 p0 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t device type identifier device addresses s a c k instruction opcode dr/wcr addresses s a c k wiper position (sent by master on sda) s a c k s t o p high-voltage write cycle 0101a3a2a1a0 1100rbra0 p0 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t device type identifier device addresses s a c k instruction opcode dr/wcr addresses s a c k s t o p 0 1 0 1 a3 a2 a1 a0 0 0 0 1 rb ra 0 0 x9269
14 fn8173.4 april 17, 2007 global xfr wiper counter register (wcr) to data register (dr) transfer wiper counter register (wcr) to data register (dr) transfer data register (dr) to wiper counter register (wcr) increment/decrement wiper counter register (wcr) notes: (1) ?mack?/?sack?: stands for the acknowledge sent by the master/slave. (2) ?a3 ~ a0?: stands for the device addresses sent by the master. (3) ?x?: indicates that it is a ?0? for testing pur pose but physically it is a ?don?t care? condition. (4) ?i?: stands for the increment operation, sda held high during acti ve scl phase (high). (5) ?d?: stands for the decrement operation, sda held low during active scl phase (high). s t a r t device type identifier device addresses s a c k instruction opcode dr/wcr addresses s a c k s t o p high-voltage write cycle 0 1 0 1a3a2a1a0 1000rbra0 0 s t a r t device type identifier device addresses s a c k instruction opcode dr/wcr addresses s a c k s t o p high-voltage write cycle 0 1 0 1a3a2a1a0 1110rbra 0 p0 s t a r t device type identifier device addresses s a c k instruction opcode dr/wcr addresses s a c k s t o p 0 1 0 1 a3 a2 a1 a0 1 1 0 1 rb ra 0 p0 s t a r t device type identifier device addresses s a c k instruction opcode dr/wcr addresses s a c k increment/decrement (sent by master on sda) s t o p 0101a3a2a1a0 001000 0 p0 i/di/d. . . .i/di/d x9269
15 fn8173.4 april 17, 2007 absolute maximum ratings temperature under bias .................... -65 c to +135 c storage temperature ......................... -65 c to +150 c voltage on scl, sda any address input with respect to v ss ................................. -1v to +7v v = | (v h - v l ) |................................................... 5.5v lead temperature (soldering, 10 seconds)........ 300 c i w (10 seconds) .................................................6ma comment stresses above those liste d under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. potentiometer characteristics (over recommended industrial (2.7v) operating conditions unless otherwise stated.) notes: (1) absolute linearity is utilized to determine actual wi per voltage versus expected volt age as determined by wiper positi on when used as a potentiometer. (2) relative linearity is utilized to determi ne the actual change in voltage between tw o successive tap positions when used as a potentiometer. it is a measure of the error in step size. (3) mi = rtot / 255 or (r h - r l ) / 255, single pot (4) during power-up v cc > v h , v l , and v w . (5) n = 0, 1, 2, ?,255; m =0, 1, 2, ?, 254. symbol parameter limits test conditions min. typ. max. units r total end to end resistance 100 k t version r total end to end resistance 50 k u version end to end resistance tolerance 20 % power rating 50 mw 25 c, each pot i w wiper current 3 ma r w wiper resistance 300 i w = 3ma @ v cc = 3v r w wiper resistance 150 i w = 3ma @ v cc = 5v v term voltage on any r h or r l pin v ss v cc vv ss = 0v noise -120 dbv ref: 1v resolution 0.4 % absolute linearity (1) 1 mi (3) r w(n)(actual) - r w(n)(expected) (5) relative linearity (2) 0.6 mi (3) r w(n + 1) - [r w(n) + mi ] (5) temperature coefficient of r total 300 ppm/ c ratiometric temp. coefficient 20 ppm/c c h /c l /c w potentiometer capacitances 10/10/25 pf see macro model i al r w , r h , r l leakage 0.1 10.0 a device in stand by. vin = v ss to v cc recommended operating conditions temp min. max. commercial 0 c+70 c industrial -40 c+85 c device supply voltage (v cc ) (4) limits x9261 5v 10% x9261-2.7 2.7v to 5.5v x9269
16 fn8173.4 april 17, 2007 d.c. operating characteristics (over the recommended operating condit ions unless otherwise specified.) endurance and data retention capacitance power-up timing power-up and down requirements the are no restrictions on the power-up or power-down conditions of v cc and the voltages applied to the poten- tiometer pins provided that v cc is always more positive than or equal to v h , v l , and v w , i.e., v cc v h , v l , v w . the v cc power-up timing spec is always in effect. a.c. test conditions notes: (6) this parameter is not 100% tested (7) t pur and t puw are the delays required from the time the (last) power supply (v cc -) is stable until the specif ic instruction can be issued. these parameters are periodically sampled and not 100% tested. symbol parameter limits test conditions min. typ. max. units i cc1 v cc supply current (active) 400 a f scl = 400khz; v cc = +6v; sda = open; (for 2-wire, active, read and volatile write states only) i cc2 v cc supply current (nonvolatile write) 15maf scl = 400khz; v cc = +6v; sda = open; (for 2-wire, active, nonvolatile write state only) i sb v cc current (standby) 5 av cc = +6v; v in = v ss or v cc ; sda = v cc ; (for 2-wire, standby state only) i li input leakage current 10 av in = v ss to v cc i lo output leakage cur- 10 av out = v ss to v cc v ih input high voltage v cc x 0.7 v cc + 1 v v il input low voltage -1 v cc x 0.3 v v ol output low voltage 0.4 v i ol = 3ma v oh output high voltage v cc - 0.8 v i oh = -1ma, v cc +3v v oh output high voltage v cc - 0.4 v i oh = -0.4ma, v cc +3v parameter min. units minimum endurance 100,000 data changes per bit per register data retention 100 years symbol test max. units test conditions c in/out (6) input / output capacitance (sda) 8 pf v out = 0v c in (6) input capacitance ( scl, wp , a3, a2, a1 and a0 )6 pf v in = 0v symbol parameter min. max. units t r v cc (6) v cc power-up rate 0.2 50 v/ms t pur (7) power-up to initiation of read operation 1 ms i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 x9269
17 fn8173.4 april 17, 2007 equivalent a.c. load circuit ac timing symbol parameter min. max. units f scl clock frequency 400 khz t cyc clock cycle time 2500 ns t high clock high time 600 ns t low clock low time 1300 ns t su:sta start setup time 600 ns t hd:sta start hold time 600 ns t su:sto stop setup time 600 ns t su:dat sda data input setup time 100 ns t hd:dat sda data input hold time 30 ns t r scl and sda rise time 300 ns t f scl and sda fall time 300 ns t aa scl low to sda data output valid time 0.9 s t dh sda data output hold time 0 ns t i noise suppression time constant at scl and sda inputs 50 ns t buf bus free time (prior to any transmission) 1200 ns t su:wpa a0, a1, a2, a3 setup time 0 ns t hd:wpa a0, a1, a2, a3 hold time 0 ns 5v 1533 100pf sda pin r h 10pf c l c l r w r total c w 25pf 10pf r l spice macromodel 3v 867 100pf sda pin x9269
18 fn8173.4 april 17, 2007 high-voltage wr ite cycle timing xdcp timing symbol table symbol parameter typ. max. units t wr high-voltage write cycle time (store instructions) 5 10 ms symbol parameter min. max. units t wrpo wiper response time after the third (last) power supply is stable 5 10 s t wrl wiper response time after instruction issued (all load instructions) 5 10 s waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x9269
19 fn8173.4 april 17, 2007 timing diagrams start and stop timing input timing output timing t su:sta t hd:sta t su:sto scl sda t r (start) (stop) t f t r t f scl sda t high t low t cyc t hd:dat t su:dat t buf scl sda t dh t aa x9269
20 fn8173.4 april 17, 2007 xdcp timing (for all load instructions) write protect and device address pins timing scl sda vwx (stop) lsb t wrl sda scl ... ... ... wp a0, a1 t su:wpa t hd:wpa (start) (stop) (any instruction) x9269
21 fn8173.4 april 17, 2007 applications information basic configurations of electronic potentiometers application circuits v r rw +v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current noninverting amplifier voltage regulator offset voltage adjustment comparator with hysterisis + ? v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + ? v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) rl l = {r 1 /(r 1 +r 2 )} v o (min) 100k 10k 10k 10k -12v +12v tl072 + ? v s v o r 2 r 1 } } 10k 10k v cc x9269
22 fn8173.4 april 17, 2007 application circuits (continued) attenuator filter inverting amplifier equivalent l-r circuit + ? v s v o r 3 r 1 v o = g v s -1/2 g +1/2 g o = 1 + r 2 /r 1 fc = 1/(2 rc) + ? v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + ? v s function generator r 2 r 4 r 1 = r 2 = r 3 = r 4 = 10k + ? v s r 2 r 1 r c } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + ? r 2 + ? r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c v o x9269
23 fn8173.4 april 17, 2007 x9269 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m m24.3 (jedec ms-013-ad issue c) 24 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.020 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.5985 0.6141 15.20 15.60 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n24 247 0 8 0 8 - rev. 1 4/06
24 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8173.4 april 17, 2007 x9269 thin shrink small outline package family (tssop) n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail ?x? end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane mdp0044 thin shrink small outline package family symbol millimeters tolerance 14 ld 16 ld 20 ld 24 ld 28 ld a 1.20 1.20 1.20 1.20 1.20 max a1 0.10 0.10 0.10 0.10 0.10 0.05 a2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 5.00 6.50 7.80 9.70 0.10 e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference rev. f 2/07 notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension ?e1? does not include interlead flash or protrusions. interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. dimensions ?d? and ?e1? are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994.

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